Optimization of Non Binary Parity Check Coefficients

This paper generalizes the method proposed by Poulliat et al. for the determination of the optimal Galois Field coefficients of a Non-Binary LDPC parity check constraint based on the binary image of the code. Optimal, or almost-optimal, parity check coefficients are given for check degree varying from 4 to 20 and Galois Field varying from GF(64) up to GF(1024). For all given sets of coefficients, no codeword of Hamming weight two exists. A reduced complexity algorithm to compute the binary Hamming weight 3 of a parity check is proposed. When the number of sets of coefficients is too high for an exhaustive search and evaluation, a local greedy search is performed. Explicit tables of coefficients are given. The proposed sets of coefficients can effectively replace the random selection of coefficients often used in NB-LDPC construction.Comment: First version submitted to IEEE Transactions on Information Theory, August the 5, 2017. Revised version, May the 5, 201

Noisy Gradient Descent Bit-Flip Decoding for LDPC Codes

A modified Gradient Descent Bit Flipping (GDBF) algorithm is proposed for decoding Low Density Parity Check (LDPC) codes on the binary-input additive white Gaussian noise channel. The new algorithm, called Noisy GDBF (NGDBF), introduces a random perturbation into each symbol metric at each iteration. The noise perturbation allows the algorithm to escape from undesirable local maxima, resulting in improved performance. A combination of heuristic improvements to the algorithm are proposed and evaluated. When the proposed heuristics are applied, NGDBF performs better than any previously reported GDBF variant, and comes within 0.5 dB of the belief propagation algorithm for several tested codes. Unlike other previous GDBF algorithms that provide an escape from local maxima, the proposed algorithm uses only local, fully parallelizable operations and does not require computing a global objective function or a sort over symbol metrics, making it highly efficient in comparison. The proposed NGDBF algorithm requires channel state information which must be obtained from a signal to noise ratio (SNR) estimator. Architectural details are presented for implementing the NGDBF algorithm. Complexity analysis and optimizations are also discussed.Comment: 16 pages, 22 figures, 2 table

Performances of a GNSS receiver for space-based applications

Space Vehicle (SV) life span depends on its station keeping capability. Station keeping is the ability of the vehicle to maintain position and orientation. Due to external perturbations, the trajectory of the SV derives from the ideal orbit. Actual positioning systems for satellites are mainly based on ground equipment, which means heavy infrastructures. Autonomous positioning and navigation systems using Global Navigation Satellite Systems (GNSS) can then represent a great reduction in platform design and operating costs. Studies have been carried out and the first operational systems, based on GPS receivers, become available. But better availability of service could be obtained considering a receiver able to process GPS and Galileo signals. Indeed Galileo system will be compatible with the current and the modernized GPS system in terms of signals representation and navigation data. The greater availability obtained with such a receiver would allow significant increase of the number of point solutions and performance enhancement. For a mid-term perspective Thales Alenia Space finances a PhD to develop the concept of a reconfigurable receiver able to deal with both the GPS system and the future Galileo system. In this context, the aim of this paper is to assess the performances of a receiver designed for Geosynchronous Earth Orbit (GEO) applications. It is shown that high improvements are obtained with a receiver designed to track both GPS and Galileo satellites. The performance assessments have been used to define the specifications of the future satellite GNSS receiver

LDPC decoder architecture for DVB-S2 and DVB-S2X standards

International audienceA particular type of conflict due to multiple-diagonal sub-matrices in the DVB-S2 parity-check matrices is known to complicate the implementation of the layered decoder architecture. The new matrices proposed in DVB-S2X no longer use such sub-matrices. For implementing a decoder compliant both with DVB-S2 and DVB-S2X, we propose an elegant solution which overcomes this conflicts relying on an efficient write disable of the memories, allowing a straightforward implementation of layered LDPC decoders. The complexity and latency are further reduced by eliminating one barrel shifter. Compared with the existing solutions, complexity is reduced without performance degradation. Keywords—Low-Density Parity-Check (LDPC) code, memory conflict, layered decoder, DVB-S2, DVB-S2X

Reliable GPS position on an unreliable hardware

International audienceThis work address the fault tolerance topic in the GPS context. Starting from a noiseless GPS receiver, redundant mechanisms can be added to design a more resilient GPS receiver in the presence of errors due to process, voltage and temperature (PVT) variations. These mechanisms are based on different layer of abstraction to guarantee a mutual trade-off of system performance (quality of the position given by the GPS receiver), hardware reliability and implementation complexity. An Application-specific integrated circuit (ASIC) will be designed with two versions of the GPS receiver: the standard version, and a complex version where fault tolerant techniques are added to make the GPS receiver more tolerant to errors

NB-LDPC check node with pre-sorted input

International audienceNon-binary low-density parity-check codes have better communication performance compared to their binary counterparts but they suffer from higher complexity, especially for the check node processing. In this paper a sorting of the input vectors based on a reliability criteria is performed prior to the check node processing. This presorting process allows the Extended Min-Sum (EMS) check node process to focus its effort mainly on the weakest inputs. Proof is given for a check node of degree 12 in GF(64) for the syndrome based algorithm with a number of computed syndromes reduced by a factor of four which directly impacts the check node complexity without performance degradation. Index Terms—NB-LDPC, Check Node, syndrome-based, EMS

A flexible implementation of a Global Navigation Satellite System receiver for on-board satellite navigation

In this paper, we present the implementation of the acquisition algorithm of a versatile Global Navigation Satellite System (GNSS) receiver for satellite applications. For versatility purpose, the choice of the receiver algorithms has been motivated by 1) their capability to fulfill the application requirements with a moderate complexity, 2) their capability of being factorized in a small set of elementary modules that can be configured and combined in various ways in order to process both GPS and Galileo current and future signals. These algorithms have been specified using SystemC, a modeling language that can be common to hardware and software flow. The use of a virtual platform for simulation allows us to identify bottleneck of the architecture and to propose algorithm modification to solve them

A Systolic LLR Generation Architecture For Non-Binary LDPC Decoders

International audienceNon-Binary LDPC codes offer higher performances than their binary counterpart but suffer from higher decoding complexity. A solution to reduce the decoding complexity is the use of the Extended Min-Sum algorithm. The first step of this algorithm requires the generation of the first n_m largest Log-Likelihood Ratio (LLR), sorted in increasing order, of each received symbol. In the case where GF(q) symbols are transmitted using a BPSK modulation, we propose a simple systolic architecture that generates the sorted list of symbols

Reducing the impact of internal upsets inside the correlation process in GPS Receivers

International audience—This paper 1 examines two approaches to deal with internal logic upsets inside correlation process used in the tracking process of GPS receivers. These upsets can be produced due to process/voltage and temperature variations coupled with increased advancement of CMOS technology. If any upset occurs when computing the correlation function during each 10 ms, then errors are propagated in tracking loops, resulting in a loss of the GPS signal tracking and a distorted position given by the receiver. Results of experiments using a GPS receiver design are presented in this paper to evaluate the performance of each method. The two proposed solutions (the Feedback freezing loop (FFL) and the Last Correct Value (LCV) methods) offer a big interest compared to the classical Triple Modular Redundancy (TMR) method since they provide the same performance as the TMR with low area complexity. This work can be extended to any system using feedback loops information